The present invention generally relates to demodulators and, more specifically, to an improved design for a fully parallel multi-channel demodulator.
Traditional digital cable, satellite and terrestrial broadcast systems utilize a large number of frequency-division multiplexed RF channels. Under conventional systems, each RF channel is typically handled by corresponding dedicated circuitry. FIG. 1 is a simplified block diagram illustrating typical circuitry used to handle RF channels. As shown in FIG. 1, a typical demodulator chip includes a channel processing block 10 for each RF channel. Each channel processing block 10 further includes an analog-digital converter (ADC) 12, a demodulator block 14 providing functionality such as automatic gain control (AGC), timing recovery, equalization and carrier recovery, and a forward error correction (FEC) block 16. For example, a digital cable receiver chip designed to accommodate two channels includes two channel processing blocks.
The architecture of the typical demodulator chip as shown in FIG. 1 has a number of problems or disadvantages. For example, the foregoing architecture is not cost effective as the number of RF channels increases. Since each channel has its own dedicated circuitry for signal processing, the corresponding circuitry remains idle when the associated channel is not active; even when the channel is active, the associated circuitry is only active during certain periods of time. As a result, silicon resources within the chip are not shared or utilized efficiently. In addition, the architecture does not scale well with silicon technology improvements. For example, as silicon technology improves to provide higher processing speed, the number of channels that can be processed remains the same.
Furthermore, FIR filters are commonly used in demodulators. FIG. 2 is a simplified schematic diagram illustrating a typical FIR filter. As shown in FIG. 2, a typical FIR filter processes an input data stream in a serial manner. In other words, the input data stream is processed sequentially by a number of multipliers. Each of these multipliers must be designed to accommodate the largest possible coefficient. Consequently, the size of each multiplier must be at least as large as the largest possible coefficient even though the largest possible coefficient may never be used. This design results in inefficient use of silicon resource.
Hence, it would be desirable to provide an improved design for a multi-channel demodulator in which the processing circuitry for RF channels is more efficiently utilized.